1. Field of the Invention
The invention generally relates to electronic circuits, and in particular, to circuits using analog-to-digital converters.
2. Description of the Related Art
An analog-to-digital converter (ADC) converts an analog signal to a digital signal. ADCs are commonly found where there is an interface with the physical world, e.g., sound, images, or in data communications where an analog signal from a cable or wireless media is digitized to be further processed or stored. Accordingly, ADCs are used in a wide variety of applications, such as data capture, data communications, hard disks, video capture, audio sampling, radar signal processing, and the like. These ADCs can be standalone, can be combined with other circuits on an integrated circuit, such as combined with a microprocessor or a digital signal processor, and can be part of a larger system, such as part of a satellite receiver, broadband network modem, phone modem, hard disk, network communication device, and the like.
A wide variety of architectures exist for an ADC. Some types of ADCs use comparator banks to convert from analog to digital. These types using comparators include Flash converters, which are also known as direct conversion ADCs. Sub-ranging converters also use comparators in the conversion process.
For example, in a Flash ADC, the conversion is accomplished by comparing an input signal to a set of threshold voltages, such as from a resistor ladder, and then establishing a digital value based on the results of the comparisons. In one example, the output of each individual comparison can assume one of two states: “1” or “0.” For example, in one arrangement, the output of the comparator is a logic “1” if the input signal is greater than the threshold and is a logic “0” otherwise. The comparator outputs are combined to form a digital word output.
In a linear ADC, it is typically desirable for the set of thresholds to be relatively evenly spaced so that there is a relatively linear relationship between the analog input and the digital output. Often, there are relatively many comparators for which a threshold is adjusted. The adjustment of a threshold to account for imperfections in the process or design for a comparator is often referred to as “trimming” the comparator.
The adjustment of thresholds of a comparator bank can be time consuming, costly, imperfect, and inconvenient. Often, the analog-to-conversion process of a signal is suspended in order to perform a calibration process. The number of comparators to be adjusted or trimmed can be relatively high and can vary with the number of output bits of the ADC. For N output bits, 2N−1 comparators are used in a Flash ADC for the detection of voltage levels. For example, in a Flash ADC with 8 binary output bits, 255 comparators are used in the comparator bank for the detection of voltage levels. In a sub-ranging ADC, the number of comparators will typically be fewer than in the Flash ADC.
FIG. 1 illustrates an example of a relatively linear mapping of an analog input to a digital output. Relatively good linearity is indicated by relatively evenly spaced thresholds along the horizontal axis, that is, thresholds thri are evenly spaced such that the relationship expressed in Equation 1 at least approximately holds.|thri−thri−1|=|thri−thri+1|  Equation 1
FIG. 2 illustrates an example of a relatively non-linear mapping of an analog input to a digital output. Relatively poor linearity is indicated by relatively unevenly spaced threshold along the horizontal axis of FIG. 2 such that the relationship expressed in Equation 2 holds, where oi indicates an offset associated with a threshold thri.|(thri+oi)−(thri−1+oi−1)|≠|(thri+oi)−(thri+1+oi+1)|  Equation 2
One common source for the offset oi is a device mismatch or a component mismatch in the embodying integrated circuit. In a non-linear ADC, the thresholds are unevenly spaced and the digital output signal is distorted with respect to the analog input signal. This distortion can be quantified by parameters such as “effective number of bits (ENOB),” or “integral non-linearity (INL),” or “differential non-linearity (DNL),” or other parameters.
FIG. 3 illustrates a conventional trimming circuit for a Flash ADC. With conventional techniques, the analog input is switched using a multiplexer to a special signal from a calibration signal generator, and a calibration circuit adjusts the trim for the comparators.
One disadvantage to this trimming technique is that the linearity required of the calibration signal generator is relatively high and should exceed the linearity that is expected of the ADC. Accordingly, the calibration signal generator is typically relatively expensive to manufacture. Another disadvantage is that while the input to the ADC is switched to the special signal, the ADC is not able to perform an analog-to-digital conversion of the analog input, which decreases the availability of the ADC to do useful work.